SH7052 Datasheet, PDF (582/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.3.8 DMAC Interface
The DMAC can be activated by reception of a message in HCAN’s mailbox 0. When DMAC
transfer ends after DMAC activation has been set, the RXPR0 and RFPR0 flags are acknowledge
signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent
to the CPU in this case. Figure 15.13 shows a DMAC transfer flowchart.
DMAC initialization
• Activation source setting
• Source/destination address settings
• Transfer count setting
• Interrupt setting
Message reception in HCAN’s
mailbox 0
DMAC activation
End of DMAC transfer?
No
Yes
DMAC transfer end bit setting
RXPR and RFPR clearing
DMAC interrupt enabled?
No
Yes
Interrupt to CPU
Clear DMAC interrupt flag
End
: Settings by user
: Processing by hardware
Figure 15.13 DMAC Transfer Flowchart
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