SH7052 Datasheet, PDF (538/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.2.4 Mailbox Configuration Register (MBCR)
The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set
mailbox (buffer) transmission/reception.
Bit: 15
14
13
12
11
10
9
8
MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —
Initial value: 0
0
0
0
0
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 9 and 7 to 0—Mailbox Setting Register (MBCR7 to 1, MBCR15 to 8): These bits set
the polarity of the corresponding mailboxes (buffers).
Bit x: MBCRx
0
1
Description
Corresponding mailbox is set for transmission
Corresponding mailbox is set for reception
(Initial value)
• Bit 8—Reserved: This bit always reads 1. The write value should always be 1.
15.2.5 Transmit Wait Register (TXPR)
The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a
transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
Bit: 15
14
13
12
11
10
9
8
TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
512