SH7052 Datasheet, PDF (546/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been
reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared
after a power-on reset or a transition to software standby mode, the program will jump to the
interrupt vector as soon as interrupts are enabled by the interrupt controller.
Bit 8: IRR0
0
1
Description
[Clearing condition]
Writing 1
Interrupt request by power-on reset or transition to software standby mode
(OVR)
(Initial value)
[Setting condition]
When reset processing is completed after power-on reset or software
standby mode transition
• Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.
• Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in HCAN sleep mode.
Bit 4: IRR12
0
1
Description
CAN bus idle state
[Clearing condition]
Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
(Initial value)
• Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been
overwritten while still unread.
Bit 1: IRR9
0
1
Description
[Clearing condition]
Clearing of all bits in UMSR (unread message status register) (Initial value)
Unread message overwrite
[Setting condition]
When UMSR (unread message status register) is set
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