SH7052 Datasheet, PDF (333/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Free-Running Counters 1A, 1B, 2A, 2B, 3, 4, 5, 11 (TCNT1A, TCNT1B, TCNT2A, TCNT2B,
TCNT3, TCNT4, TCNT5, TCNT11): Free-running counters 1A, 1B, 2A, 2B, 3, 4, 5, and 11
(TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, TCNT11) are 16-bit
readable/writable registers that count on an input clock. When the bits corresponding to the timer
start register 1, 3 (TSTR1, TSTR3) are set to 1, these counters start to count. The input clock is
selected with prescaler register 1 (PSCR1) and the timer control register (TCR).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit name:
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The TCNT1A, TCNT1B, TCNT2A, and TCNT2B counters are cleared if incremented during
counter clear trigger input from channel 10.
TCNT3 to TCNT5 counter clearing is performed by a compare-match with the corresponding
general register, according to the setting in TIOR.
When one of counters TCNT1A/1B/2A/2B/3/4/5/11 overflows (from H'FFFF to H'0000), the
overflow flag (OVF) for the corresponding channel in the timer status register (TSR) is set to 1.
TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 can only be
accessed by a word read or write.
TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, TCNT5, and TCNT11 are initialized
to H'0000 by a power-on reset, and in hardware standby mode and software standby mode.
TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on external
clock (TCLKA or TCLKB) input.
TCNT1A, TCNT1B, TCNT2A, TCNT2B, TCNT3, TCNT4, and TCNT5 can count on an external
interrupt clock (TI10) (AGCK) generated in channel 10 and on a channel 10 multiplied clock
(AGCKM).
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