SH7052 Datasheet, PDF (549/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning
interrupt requests caused by the receive error counter.
Bit 12: IMR4
0
1
Description
REC error warning interrupt request (OVR) by IRR4 to CPU enabled
REC error warning interrupt request (OVR) by IRR4 to CPU disabled
(Initial value)
• Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error
warning interrupt requests caused by the transmit error counter.
Bit 11: IMR3
0
1
Description
TEC error warning interrupt request (OVR) by IRR3 to CPU enabled
TEC error warning interrupt request (OVR) by IRR3 to CPU disabled
(Initial value)
• Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame
reception interrupt requests.
Bit 10: IMR2
0
Description
Remote frame reception interrupt request (OVR) by IRR2 to CPU enabled
1
Remote frame reception interrupt request (OVR) by IRR2 to CPU disabled
(Initial value)
• Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception
interrupt requests.
Bit 9: IMR1
0
1
Description
Message reception interrupt request (RM) by IRR1 to CPU enabled
Message reception interrupt request (RM) by IRR1 to CPU disabled
(Initial value)
• Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
• Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.
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