SH7052 Datasheet, PDF (142/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.1.2 Block Diagram
Figure 8.1 shows the BSC block diagram.
On-chip
memory
control unit
WAIT
Wait
control unit
RAMER
Bus interface
WCR
CS0 to CS3
Area
control unit
BCR1
BCR2
RD
WRH, WRL
Memory
control unit
BSC
WCR: Wait control register
RAMER: RAM emulation register
BCR1: Bus control register 1
BCR2: Bus control register 2
Figure 8.1 BSC Block Diagram
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