SH7052 Datasheet, PDF (587/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the A/D converter.
AVcc
AVref
AVss
A/D0
10-bit D/A
Module data bus
ADDR0 to ADDR1
ATU0
ADTRG0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
A/D1
Sample-and-
hold circuit
+
–
Comparator
A/D conversion
control circuit
Module data bus
10-bit D/A
ADDR12 to ADDR15
Internal data bus
ADI0 interrupt signal
Internal data bus
AN12
AN13
AN14
AN15
ATU0
Sample-and-
hold circuit
+
–
Comparator
A/D conversion
control circuit
ADI1 interrupt signal
ADCR0, ADCR1: A/D control registers 0 and 1
ADCSR0, ADCSR1: A/D control/status registers 0 and 1
ADDR0 to ADDR15: A/D data registers 0 to 15
ADTRGR0:
A/D trigger register0
Figure 16.1 A/D Converter Block Diagram
561