SH7052 Datasheet, PDF (866/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

24.3.11 AUD Timing
Table 24.16 shows AUD timing.
Table 24.16 AUD Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 85°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing flash EEPROM, T_a = –40°C to 85°C.
Item
Symbol Min
Max
Unit Figures
AUDRST pulse width (Branch trace
t _AUDRSTW
20
—
mode)
t _cyc
Figure 24.20
AUDRST pulse width (RAM monitor
t _AUDRSTW
5
—
mode)
t _RMCYC
AUDMD setup time (Branch trace mode) t_AUDMDS
20
—
t _cyc
AUDMD setup time (RAM monitor mode) t_AUDMDS
5
—
t _RMCYC
Branch trace clock cycle
t _RTCYC
2
2
t _cyc
Figure 24.21
Branch trace clock duty
t _RTCKW
40
60
%
Branch trace data delay time
t _RTDD
—
40
ns
Branch trace data hold time
t _RTDH
0
—
ns
Branch trace SYNC delay time
t _RTSD
—
40
ns
Branch trace SYNC hold time
t _RTSH
0
—
ns
RAM monitor clock cycle
t _RMCYC
100
—
ns
Figure 24.22
RAM monitor clock low pulse width
t _RMCKW
45
—
ns
RAM monitor output data delay time
t _RMDD
7
t_RMCYC – 20 ns
RAM monitor output data hold time
t _RMDHD
5
—
ns
RAM monitor input data setup time
t _RMDS
20
—
ns
RAM monitor input data hold time
t _RMDH
5
—
ns
RAM monitor SYNC setup time
t _RMSS
20
—
ns
RAM monitor SYNC hold time
t _RMSH
5
—
ns
Load conditions: AUDCK (in branch trace): C_L = 30 pF: Other than above C_L = 100 pF
AUDSYNC, AUDATA3 to AUDATA0: C_L = 100 pF
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