SH7052 Datasheet, PDF (741/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Start
*1
Set SWE1 bit in FLMCR1
Wait: t_SSWE
n=1
Set EBR1 and EBR2
*3
Enable WDT
Set ESU1 bit in FLMCR1
Wait: tSESU
Set E1 bit in FLMCR1
Wait: tSE
Clear E1 bit in FLMCR1
Wait: tCE
Clear ESU1 bit in FLMCR1
Wait: tCESU
Disable WDT
Set EV1 bit in FLMCR1
Wait: tSEV
Set block start address to verify address
H'FF dummy write to verify address
Increment
address
NG
Wait: tSEVR
Read verify data
Verify data = all "1"?
OK
Last address of block?
OK
Clear EV1 bit in FLMCR1
*2
NG
Wait: tCEV
NG
*4
End of
erasing of all erase
blocks?
OK
Clear SWE1 bit in FLMCR1
Wait: tCSWE
End of erasing
Erasing must be performed
in block units.
n←n+1
Clear EV1 bit in FLMCR1
Wait: tCEV
NG
n ≥ 100?
OK
Clear SWE1 bit in FLMCR1
Wait: tCSWE
Erase failure
Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1 and EBR2. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 20.15 Erase/Erase-Verify Flowchart
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