SH7052 Datasheet, PDF (115/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0.
Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting
H'F. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1,
DMAC2 and DMAC3, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules are set to
the same priority rank.
IPRA, IPRC to IPRL are initialized to H'0000 by a reset and in hardware standby mode. They are
not initialized in software standby mode.
6.3.2 Interrupt Control Register (ICR)
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin
NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. A reset and hardware
standby mode initialize ICR but the software standby mode does not.
Bit: 15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
Initial value:
*
0
0
0
0
0
0
0
R/W: R
—
—
—
—
—
—
R/W
Bit: 7
6
5
4
3
2
1
0
IRQ0S IRQ1S IRQ2S IRQ3S 



Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W




Note: * When NMI input is high: 1; when NMI input is low: 0
• Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit
can be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
• Bits 14 to 9—Reserved: These bits always read 0. The write value should always be 0.
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