SH7052 Datasheet, PDF (482/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.2.8 Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to BRR. BRR is initialized to H'FF by a power-on reset and in
hardware standby mode. It is not initialized by a manual reset, and in software standby mode.
Each channel has independent baud rate generator control, so different values can be set for each
channel.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 14.3 lists examples of BRR settings in the asynchronous mode; table 14.4 lists examples of
BBR settings in the clock synchronous mode.
The BRR setting is calculated as follows:
Asynchronous mode:
N=
P_φ
64 × 2^2n–1 × B
× 10⁶ – 1
Synchronous mode:
N=
P_φ
× 10⁶ – 1
8 × 2^2n–1 × B
B: Bit rate (bits/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
Pφ: Peripheral module operating frequency (MHz) (1/2 of system clock)
n: Baud rate generator input clock (n = 0 to 3)
(See the following table for the clock sources and value of n.)
SMR Settings
n
Clock Source
CKS1
CKS2
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
456