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SH7052 Datasheet, PDF (456/919 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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13.2 Register Descriptions
13.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to
operate or halt the channel 0 and channel 1 counters (CMCNT). It is initialized to H'0000 by a
power-on reset and in the standby modes.
Bit: 15
14
13
12
11
10
9
8
â
â
â
â
â
â
â
â
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
â
â
â
â
â
â
STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
⢠Bits 15 to 2âReserved: These bits always read 0. The write value should always be 0.
⢠Bit 1âCount Start 1 (STR1): Selects whether to operate or halt compare match timer counter
1.
Bit 1: STR1
0
1
Description
CMCNT1 count operation halted
CMCNT1 count operation
(Initial value)
⢠Bit 0âCount Start 0 (STR0): Selects whether to operate or halt compare match timer counter
0.
Bit 0: STR0
0
1
Description
CMCNT0 count operation halted
CMCNT0 count operation
(Initial value)
430
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