SH7052 Datasheet, PDF (278/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 1—Cycle Register Compare-Match Flag 6B/7B (CMF6B/CMF7B): Status flag that
indicates CYLRxB compare-match.
Bit 1: CMFxB
0
1
x = 6 or 7
Description
[Clearing condition]
(Initial value)
When CMFxB is read while set to 1, then 0 is written to CMFxB
[Setting conditions]
• When TCNTxB = CYLRxB (in non-complementary PWM mode)
• When TCNT6B = H'0000 in a down-count (in complementary PWM mode)
• Bit 0—Cycle Register Compare-Match Flag 6A/7A (CMF6A/CMF7A): Status flag that
indicates CYLRxA compare-match.
Bit 0: CMFxA
0
1
x = 6 or 7
Description
[Clearing condition]
(Initial value)
When CMFxA is read while set to 1, then 0 is written to CMFxA
[Setting conditions]
• When TCNTxA = CYLRxA (in non-complementary PWM mode)
• When TCNT6A = H'0000 in a down-count (in complementary PWM mode)
Timer Status Register 8 (TSR8)
TSR8 indicates the channel 8 one-shot pulse status.
Bit:
Initial value:
R/W:
15
14
13
12
11
OSF8P OSF8O OSF8N OSF8M OSF8L
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
10
OSF8K
0
R/(W)*
9
OSF8J
0
R/(W)*
8
OSF8I
0
R/(W)*
Bit:
Initial value:
R/W:
7
6
5
OSF8H OSF8G OSF8F
0
0
0
R/(W)* R/(W)* R/(W)*
4
OSF8E
0
R/(W)*
3
OSF8D
0
R/(W)*
2
OSF8C
0
R/(W)*
1
0
OSF8B OSF8A
0
0
R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
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