SH7052 Datasheet, PDF (405/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Sample Setup Procedure for Interval Timer Operation: An example of the setup procedure for
interval timer operation is shown in figure 10.58.
1. Set the first-stage counter clock ø' in prescaler register 1 (PSCR1).
2. Set the ITVE bit to be used in the interval interrupt request register (ITVRR) to 1. An interrupt
request can be sent to the CPU when the corresponding bit changes to 1 in the channel 0 free-
running counter (TCNT0).
To start A/D converter sampling, set the ITVA bit to be used in ITVRR to 1.
3. Set bit 0 to 1 in the timer start register (TSTR) to start TCNT0.
Start
Select counter clock 1
Set interval
2
Start counter
3
Interrupt request to CPU
or start of A/D0 sampling
Figure 10.58 Sample Setup Procedure for Interval Timer Operation
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