SH7052 Datasheet, PDF (102/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.1.2 Block Diagram
Figure 6.1 is a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
Input
control
CPU/
DMAC
request
judg-
ment
Priority
ranking
judg-
ment
Com-
parator
UBC
DMAC
ATU-II
CMT
A/D
SCI
WDT
HCAN
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR
IPR
ISR
IPRA, IPRC to IPRL
Module bus
Bus
interface
INTC
UBC: User break controller
DMAC: Direct memory access controller
ATU-II: Advanced timer unit
CMT: Compare match timer
A/D: A/D converter
SCI: Serial communication interface
WDT: Watchdog timer
HCAN: Hitachi controller area network
ICR: Interrupt control register
ISR: IRQ status register
IPRA, IPRC to IPRL: Interrupt priority level setting
registers A, C to L
SR: Status register
Figure 6.1 INTC Block Diagram
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