SH7052 Datasheet, PDF (13/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.3.3 IRQ Status Register (ISR) .................................................................................... 90
6.4 Interrupt Operation ............................................................................................................ 92
6.4.1 Interrupt Sequence................................................................................................ 92
6.4.2 Stack after Interrupt Exception Processing .......................................................... 94
6.5 Interrupt Response Time ................................................................................................... 95
6.6 Data Transfer with Interrupt Request Signals ................................................................... 97
6.6.1 Handling CPU Interrupt Sources, but Not DMAC Activating Sources ............... 97
6.6.2 Handling DMAC Activating Sources but Not CPU Interrupt Sources ................ 97
Section 7 User Break Controller (UBC) ..................................................................... 99
7.1 Overview............................................................................................................................ 99
7.1.1 Features ................................................................................................................ 99
7.1.2 Block Diagram...................................................................................................... 100
7.1.3 Register Configuration ......................................................................................... 101
7.2 Register Descriptions......................................................................................................... 101
7.2.1 User Break Address Register (UBAR)................................................................. 101
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 102
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 104
7.2.4 User Break Control Register (UBCR).................................................................. 106
7.3 Operation ........................................................................................................................... 107
7.3.1 Flow of the User Break Operation........................................................................ 107
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 109
7.3.3 Program Counter (PC) Values Saved ................................................................... 109
7.4 Examples of Use................................................................................................................ 110
7.4.1 Break on CPU Instruction Fetch Cycle ................................................................ 110
7.4.2 Break on CPU Data Access Cycle........................................................................ 111
7.4.3 Break on DMA Cycle........................................................................................... 111
7.5 Usage Notes ....................................................................................................................... 112
7.5.1 Simultaneous Fetching of Two Instructions......................................................... 112
7.5.2 Instruction Fetch at Branches ............................................................................... 112
7.5.3 Contention between User Break and Exception Processing ................................ 113
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 113
7.5.5 User Break Trigger Output................................................................................... 113
7.5.6 Module Standby.................................................................................................... 114
Section 8 Bus State Controller (BSC) ......................................................................... 115
8.1 Overview............................................................................................................................ 115
8.1.1 Features ................................................................................................................ 115
8.1.2 Block Diagram...................................................................................................... 116
8.1.3 Pin Configuration ................................................................................................. 117
8.1.4 Register Configuration ......................................................................................... 117
8.1.5 Address Map ........................................................................................................ 118
8.2 Description of Registers .................................................................................................... 122
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