SH7052 Datasheet, PDF (461/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 13.4 CMF Set Timing
13.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared by writing a 0 to it after reading a 1. Figure 13.5
shows the timing when the CMF bit is cleared by the CPU.
CMCSR write cycle
T1
T2
Pφ
CMF
Figure 13.5 Timing of CMF Clear by the CPU
435