SH7052 Datasheet, PDF (373/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Pø
TCNT1A
Clock
TCNT1A 0000
0001
Edge detection signal
(from channel 0)
0002
0003
0004
0005
5678
5679
567A
567B
567C
567D
567E
OSBR1
0003
567A
Figure 10.20 Twin-Capture Operation
10.3.9 PWM Timer Function
Channels 6 and 7 can be used unconditionally as PWM timers using external pins (TO6A to
TO6D, TO7A to TO7D).
In channels 6 and 7, when the corresponding bit is set in the timer start register (TSTR) and the
free-running counter (TCNT) is started, the counter counts up until its value matches the
corresponding cycle register (CYLR). When TCNT matches CYLR, it is cleared to H'0001 and
starts counting up again from that value. At this time, 1 is output from the corresponding external
pin. An interrupt request can be sent to the CPU by setting the corresponding bit in the timer
interrupt enable register (TIER). If a value has been set in the duty register (DTR), when TCNT
matches DTR, 0 is output to the corresponding external pin. If the DTR value is H'0000, the
output does not change (0% duty). A duty of 100% is specified by setting DTR = CYLR. Do not
set a value in DTR that will result in the condition DTR > CYLR.
Channels 6 and 7 have buffers (BFR); the BFR value is transferred to DTR when TCNT matches
CYLR. The duty value written into BFR is reflected in the output value in the cycle following that
in which BFR is written to.
An example of PWM timer operation is shown in figure 10.21.
In the example in figure 10.21, H'0004 is set in channel 6 CYLR6A, and H'0002, H'0000 (0%),
H'0004 (100%), and H'0001 in BFR6A.
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