SH7052 Datasheet, PDF (602/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

16.3 CPU Interface
A/D data registers 0 to 15 (ADDR0 to ADDR15) are 16-bit registers, but they are connected to the
CPU by an 8-bit data bus. Therefore, the upper and lower bytes must be read separately.
To prevent the data being changed between the reads of the upper and lower bytes of an A/D data
register, the lower byte is read via a temporary register (TEMP). The upper byte can be read
directly.
Data is read from an A/D data register as follows. When the upper byte is read, the upper-byte
value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the CPU.
When performing byte-size reads on an A/D data register, always read the upper byte before the
lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect
data may be obtained. If a word-size read is performed on an A/D data register, reading is
performed in upper byte, lower byte order automatically.
Figure 16.2 shows the data flow for access to an A/D data register.
Upper-byte read
CPU
(H'AA)
Lower-byte read
CPU
(H'40)
Bus
interface
Module data bus
ADDRnH
(H'AA)
TEMP
(H'40)
ADDRnL
(H'40)
Bus
interface
Module data bus
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
Figure 16.2 A/D Data Register Access Operation (Reading H'AA40)
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