SH7052 Datasheet, PDF (166/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Selectable bus modes: Cycle-steal mode or burst mode
• Fixed DMAC channel priority ranking
• CPU can be interrupted when the specified number of data transfers are complete.
9.1.2 Block Diagram
Figure 9.1 is a block diagram of the DMAC.
On-chip ROM
On-chip RAM
On-chip
peripheral
module
HCAN
ATU-II
SCI0 to SCI4
A/D converter 0, 1
DEIn
DMAC module
Circuit
control
SARn
Register
control
Activation
control
DARn
DMATCRn
CHCRn
Request
priority
control
DMAOR
External
ROM
External
RAM
External I/O
(memory
mapped)
140
Bus interface
Bus state
controller
SARn: DMAC source address register
DARn: DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
DMAOR: DMAC operation register
n: 0, 1, 2, 3
Figure 9.1 DMAC Block Diagram