SH7052 Datasheet, PDF (563/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 15.4 BCR Setting Limits
Name
Time segment 1
Time segment 2
Baud rate prescaler
Abbreviation
TSEG1
TSEG2
BRP
Min. Value
4
2
2
Sample point
SAM
1
Re-synchronization jump width SJW
1
Max. Value
16
8
128
3
4
Unit
TQ
TQ
System
clock
Point
TQ
Settable Variable Limits
• The bit width consists of the total of the settable time quanta (TQ). TQ (number of system
clocks) is determined by the baud rate prescaler (BRP).
TQ = (2*(BRP + 1))/(f_CLK)
f_CLK = Pφ
• The minimum value of SJW is stipulated in the CAN specifications.
4 ≥ SJW ≥ 1
• The minimum value of TSEG1 is stipulated in the CAN specifications.
TSEG1 ≥ TSEG2
• The minimum value of TSEG2 is stipulated in the CAN specifications.
TSEG2 ≥ (1 + SJW)
The following formula is used to calculate the baud rate.
Bit rate [b/s] =
f_CLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Note: f_CLK = Pφ (peripheral clock: φ/2]
The BCR values are used for BRP, TSEG1, and TSEG2.
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