SH7052 Datasheet, PDF (12/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Section 5 Exception Processing .................................................................................... 61
5.1 Overview............................................................................................................................ 61
5.1.1 Types of Exception Processing and Priority ........................................................ 61
5.1.2 Exception Processing Operations ......................................................................... 62
5.1.3 Exception Processing Vector Table...................................................................... 63
5.2 Resets................................................................................................................................. 65
5.2.1 Types of Reset ...................................................................................................... 65
5.2.2 Power-On Reset.................................................................................................... 65
5.2.3 Manual Reset........................................................................................................ 66
5.3 Address Errors ................................................................................................................... 67
5.3.1 Address Error Sources.......................................................................................... 67
5.3.2 Address Error Exception Processing.................................................................... 68
5.4 Interrupts............................................................................................................................ 68
5.4.1 Interrupt Sources .................................................................................................. 68
5.4.2 Interrupt Priority Level......................................................................................... 69
5.4.3 Interrupt Exception Processing ............................................................................ 69
5.5 Exceptions Triggered by Instructions................................................................................ 70
5.5.1 Types of Exceptions Triggered by Instructions.................................................... 70
5.5.2 Trap Instructions .................................................................................................. 70
5.5.3 Illegal Slot Instructions ........................................................................................ 71
5.5.4 General Illegal Instructions .................................................................................. 71
5.6 When Exception Sources Are Not Accepted..................................................................... 72
5.7 Stack Status after Exception Processing Ends................................................................... 73
5.8 Usage Notes ....................................................................................................................... 74
5.8.1 Value of Stack Pointer (SP).................................................................................. 74
5.8.2 Value of Vector Base Register (VBR) ................................................................. 74
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 74
Section 6 Interrupt Controller (INTC)......................................................................... 75
6.1 Overview............................................................................................................................ 75
6.1.1 Features ................................................................................................................ 75
6.1.2 Block Diagram...................................................................................................... 76
6.1.3 Pin Configuration ................................................................................................. 77
6.1.4 Register Configuration ......................................................................................... 77
6.2 Interrupt Sources................................................................................................................ 78
6.2.1 NMI Interrupts...................................................................................................... 78
6.2.2 User Break Interrupt ............................................................................................. 78
6.2.3 IRQ Interrupts ...................................................................................................... 78
6.2.4 On-Chip Peripheral Module Interrupts ................................................................ 79
6.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 79
6.3 Description of Registers .................................................................................................... 88
6.3.1 Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL) ............................. 88
6.3.2 Interrupt Control Register (ICR) .......................................................................... 89
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