SH7052 Datasheet, PDF (180/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.3.2 DMA Transfer Requests
DMA transfer requests are generated in either the data transfer source or destination. Transfers can
be requested in two modes: auto-request and on-chip peripheral module request. The request mode
is selected in the RS4 to RS0 bits of DMA channel control registers 0 to 3 (CHCR0 to CHCR3).
Auto-Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bits of CHCR0 to CHCR3 and the DME bit of
DMAOR are set to 1, the transfer begins (so long as the TE bits of CHCR0 to CHCR3 and the
NMIF and AE bits of DMAOR are all 0).
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.2,
there are 26 transfer request signals: 12 from the advanced timer unit (ATU-II), which are
compare match or input capture interrupts; the receive data full interrupts (RXI) and transmit data
empty interrupts (TXI) of the five serial communication interfaces (SCI); the receive interrupt of
HCAN; and the A/D conversion end interrupts (ADI) of the three A/D converters. When DMA
transfers are enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon
the input of a transfer request signal.
When the transfer request is set to RXI (transfer request because the SCI’s receive data register is
full), the transfer source must be the SCI’s receive data register (RDR). When the transfer request
is set to TXI (transfer request because the SCI’s transmit data register is empty), the transfer
destination must be the SCI’s transmit data register (TDR). If the transfer request is set to the A/D
converter, the data transfer source must be the A/D converter register; if set to HCAN, the transfer
source must be HCAN message data.
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