SH7052 Datasheet, PDF (861/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

24.3.8 Serial Communication Interface Timing
Table 24.13 shows serial communication interface timing.
Table 24.13 Serial Communication Interface Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC1 = 5.0 V ±0.5 V/3.3 V ±0.3 V,
PV_CC2 = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, AV_ref = 4.5 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –40°C to 85°C.
When PV_CC1 = 3.3 V ±0.3 V, V_CC = PV_CC1.
When writing or erasing flash EEPROM, T_a = –40°C to 85°C.
Item
Clock cycle
Clock cycle (clock sync)
Clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
Receive data hold time
Symbol
t _scyc
t _scyc
t _sckw
t _sckr
t _sckf
t _TxD
t _RxS
t _RxH
Min
8
12
0.4
—
—
—
100
100
Max
—
—
0.6
3.0
3.0
100
—
—
Unit
t _cyc
t _cyc
t _scyc
t _cyc
t _cyc
ns
ns
ns
Figures
Figure 24.15
Figure 24.16
[Operating precautions]
The inputs and outputs are asynchronous in start-stop synchronous mode, but as shown in figure
24.16, the receive data are judged to have been changed at CK clock rise (two-clock intervals).
The transmit signals change with a reference of CK clock rise (two-clock intervals).
SCK0 to SCK2
t_sckw
V_IH
V_IH
V_IL
t_sckr
V_IH
V_IL
t_scyc
t_sckf
V_IH
V_IL
Figure 24.15 SCI Input/Output Timing
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