SH7052 Datasheet, PDF (489/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode)
Pφ (MHz)
10
12
14
16
18
20
External Input Clock (MHz)
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
Maximum Bit Rate (Bits/s)
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3
14.2.9 Serial Direction Control Register (SDCR)
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
DIR
—
—
—
Initial value: 1
1
1
1
0
0
1
0
R/W: R
R
R
R
R/W
R
R
R
The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer.
With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the
communication mode. With a 7-bit data length, LSB-first transfer must be selected. The
description in this section assumes LSB-first transfer.
SDCR is initialized to H'F2 by a power-on reset and in the hardware standby mode. It is not
initialized by a manual reset, and in software standby mode.
• Bits 7 to 4—Reserved: The write value must always be 1. Operation cannot be guaranteed if 0
is written.
• Bit 3—Data Transfer Direction (DIR): Selects the serial/parallel conversion format. Valid for
an 8-bit transmit/receive format.
Bit 3: DIR
0
1
Description
TDR contents are transmitted in LSB-first order
Receive data is stored in RDR in LSB-first order
TDR contents are transmitted in MSB-first order
Receive data is stored in RDR in MSB-first order
(Initial value)
• Bit 2—Reserved: This bit always reads 0. Operation cannot be guaranteed if 1 is written.
• Bit 1—Reserved: This bit always reads 1, and cannot be modified.
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