SH7052 Datasheet, PDF (114/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

6.3 Description of Registers
6.3.1 Interrupt Priority Registers A, C to L (IPRA, IPRC to IPRL)
Interrupt priority registers A, C to L (IPRA, IPRC to IPRL) are 16-bit readable/writable registers
that set priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.
Correspondence between interrupt request sources and each of the IPRA, IPRC to IPRL bits is
shown in table 6.4.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA, IPRC to IPRL
Register
Interrupt priority register A
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register J
Interrupt priority register K
Interrupt priority register L
15 to 12
IRQ0
DMAC0, 1
ATU03
ATU13
ATU31
ATU51
ATU81
ATU91
ATU11
SCI0
SCI4
Bits
11 to 8
7 to 4
IRQ1
IRQ2
DMAC2, 3
ATU01
ATU04
ATU11
ATU21
ATU22
ATU32
ATU41
ATU52
ATU6
ATU82
ATU83
ATU92
ATU101
CMT0, A/D0 CMT1, A/D1
SCI1
SCI2
HCAN
WDT
3 to 0
IRQ3
ATU02
ATU12
ATU23
ATU42
ATU7
ATU84
ATU102

SCI3

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