SH7052 Datasheet, PDF (743/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
20.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1,
EBR1, and EBR2 settings are retained in the error-protected state. (See table 20.10.)
Table 20.10 Hardware Protection
Item
FWE pin protection
Reset/standby
protection
Description
• When a low level is input to the FWE pin,
FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/erase-
protected state is entered.
• In a power-on reset (including a WDT
power-on reset) and in standby mode,
FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/erase-
protected state is entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section. Do not execute a
reset during programming or erasing, as
the values in the flash memory are not
guaranteed if this is done. In this case,
execute an erase, then execute
programming once again.
Functions
Program Erase
Yes
Yes
Yes
Yes
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