SH7052 Datasheet, PDF (736/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
A transition to program-verify mode is made by setting the PV1 bit in FLMCR1 and waiting for
an interval of t_SPV. Before reading in program-verify mode, perform a dummy write of H'FF data to
the read addresses, and then wait for an interval of t_SPVR or longer. When the flash memory is read
in this state (verify data is read in longword units), the data at the latched address is read. Next, the
written data is compared with the verify data, and reprogram data is computed (see figures 20.13
and 20.14) and transferred to the reprogram data area. After 128 bytes of data have been verified,
exit program-verify mode. Program-verify mode is exited by clearing the PV1 bit in FLMCR1,
then clearing the SWEn bit after an interval of t_CPV or longer, and waiting for an interval of t_CSWE or
longer. If reprogramming is necessary, set program mode again, and repeat the program/program-
verify sequence as before. However, ensure that the program/program-verify sequence is not
repeated more than 1,000 times on the same bits.
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