SH7052 Datasheet, PDF (550/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4: IMR12
0
1
Description
Bus operation interrupt request (OVR) by IRR12 to CPU enabled
Bus operation interrupt request (OVR) by IRR12 to CPU disabled
(Initial value)
• Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1: IMR9
0
Description
Unread message overwrite interrupt request (OVR) by IRR9 to CPU enabled
1
Unread message overwrite interrupt request (OVR) by IRR9 to CPU
disabled
(Initial value)
• Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0: IMR8
0
1
Description
Mailbox empty interrupt request (SLE) by IRR8 to CPU enabled
Mailbox empty interrupt request (SLE) by IRR8 to CPU disabled
(Initial value)
15.2.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
524