SH7052 Datasheet, PDF (53/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Word or longword immediate data is not located in the instruction code, but instead is stored in a
memory table. An immediate data transfer instruction (MOV) accesses the memory table using the
PC relative addressing mode with displacement.
2.3 Instruction Features
2.3.1 RISC-Type Instruction Set
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per Cycle: The microprocessor can execute basic instructions in one cycle using
the pipeline system. Instructions are executed in 25 ns at 40 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data (table 2.2).
Table 2.2 Sign Extension of Word Data
SH7052F/SH7053F/SH7054F
CPU
Description
MOV.W @(disp,PC),R1
ADD
R1,R0
.........
.DATA.W H'1234
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Note: @(disp, PC) accesses the immediate data.
Example of Conventional CPU
ADD.W #H'1234,R0
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions.
With a delayed branch instruction, the branch is taken after execution of the instruction following
the delayed branch instruction (table 2.3). This reduces pipeline disruption when branching. There
are two types of conditional branch instructions: delayed branch instructions and ordinary branch
instructions.
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