SH7052 Datasheet, PDF (152/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit 1: SW1
0
1
Bit 0: SW0
0
1
Description
No CS1 space CS assert extension
CS1 space CS assert extension
Description
No CS0 space CS assert extension
CS0 space CS assert extension
(Initial value)
(Initial value)
8.2.3 Wait Control Register (WCR)
Bit:
Initial value:
R/W:
15
W33
1
R/W
14
W32
1
R/W
13
W31
1
R/W
12
W30
1
R/W
11
W23
1
R/W
10
W22
1
R/W
9
W21
1
R/W
8
W20
1
R/W
Bit:
Initial value:
R/W:
7
W13
1
R/W
6
W12
1
R/W
5
W11
1
R/W
4
W10
1
R/W
3
W03
1
R/W
2
W02
1
R/W
1
W01
1
R/W
0
W00
1
R/W
WCR is a 16-bit readable/writable register that specifies the number of wait cycles for each CS
space.
WCR1 is initialized to H'FFFF by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
• Bits 15 to 12—CS3 Space Wait Specification (W33, W32, W31, W30): These bits specify the
number of waits for CS3 space access.
Bit 15:
W33
0
0
1
Bit 14:
W32
0
0
⋅⋅⋅
1
Bit 13:
W31
0
0
1
Bit 12:
W30
0
1
1
Description
No wait (external wait input disabled)
1 wait external wait input enabled
15 wait external wait input enabled
(Initial value)
126