SH7052 Datasheet, PDF (158/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

When the wait is specified by software using WCR, the wait input WAIT signal from outside is
sampled. Figure 8.5 shows the WAIT signal sampling. The WAIT signal is sampled at the clock
rise one cycle before the clock rise when the T_w state shifts to the T₂ state. When using external
waits, use a WCR setting of 1 state or more when extending CS assertion, and 2 states or more
otherwise.
T₁
T_W
T_W
T_W0
T₂
CK
Address
CSn
Read
RD
Data
Write
WRH, WRL
Data
WAIT
Figure 8.5 Wait State Timing of External Space Access (Two Software Wait States + WAIT
Signal Wait State)
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