SH7052 Datasheet, PDF (598/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 4—A/D Continuous Scan (ADCS): Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is selected. See section 16.4.2, Scan Mode,
for details.
Bit 4:
ADCS
0
1
Description
Single-cycle scan
Continuous scan
(Initial value)
• Bits 3 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
16.2.4 A/D Control/Status Register 1 (ADCSR1)
A/D control/status register 1 (ADCSR1) is an 8-bit readable/writable register whose functions
include selection of the A/D conversion mode for A/D1.
ADCSR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7
6
5
ADF ADIE ADM1
Initial value: 0
0
0
R/W: R/(W)* R/W R/W
Note: * Only 0 can be written, to clear the flag.
4
ADM0
0
R/W
3
CH3
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
• Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7:
ADF
0
1
Description
Indicates that A/D1 is performing A/D conversion, or is in the idle state (Initial value)
[Clearing conditions]
• When ADF is read while set to 1, then 0 is written to ADF
• When the DMAC is activated by ADI2
Indicates that A/D1 has finished A/D conversion, and the digital value has been
transferred to ADDR
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When all set A/D conversions end
The operation of the A/D converter after ADF is set to 1 differs between single mode and scan
mode.
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