SH7052 Datasheet, PDF (740/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

After the elapse of the erase time, erase mode is exited. In exiting erase mode, the E1 bit in
FLMCR1 is cleared, then after an interval of t_CE or longer the ESU1 bit is cleared, and after a
further interval of t_CESU or longer the watchdog timer is halted.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
be erased to all “0”) is not necessary before starting the erase procedure.
20.7.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
A transition to erase-verify mode is made by setting the E1 bit in FLMCR1 and waiting for an
interval of t_SEV. Before reading in erase-verify mode, perform a dummy write of H'FF data to the
read addresses, and then wait for an interval of t_SEVR or longer. When the flash memory is read in
this state (verify data is read in longword units), the data at the latched address is read. If the read
data has been erased (all “1”), a dummy write is performed to the next address, and erase-verify is
performed. If there are any unerased blocks, make a 1-bit setting for the flash memory area to be
erased, and repeat the erase/erase-verify sequence as before. Ensure that the operation is not
repeated more than 100 times. When verification is completed, exit erase-verify mode. Erase-
verify mode is exited by clearing the EV1 bit in FLMCR1, then waiting for an interval of t_CEV or
longer. If erasure has been completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If
there are any unerased blocks, make a 1-bit setting for the flash memory area to be erased, and
repeat the erase/erase-verify sequence as before.
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