SH7052 Datasheet, PDF (19/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 514
15.2.8 Abort Acknowledge Register (ABACK).............................................................. 515
15.2.9 Receive Complete Register (RXPR) .................................................................... 516
15.2.10 Remote Request Register (RFPR)........................................................................ 517
15.2.11 Interrupt Register (IRR) ....................................................................................... 517
15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 521
15.2.13 Interrupt Mask Register (IMR) ............................................................................ 522
15.2.14 Receive Error Counter (REC) .............................................................................. 524
15.2.15 Transmit Error Counter (TEC) ............................................................................. 525
15.2.16 Unread Message Status Register (UMSR) ........................................................... 525
15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........................................... 526
15.2.18 Message Control (MC0 to MC15)........................................................................ 527
15.2.19 Message Data (MD0 to MD15)............................................................................ 531
15.3 Operation ........................................................................................................................... 533
15.3.1 Hardware Reset and Software Reset .................................................................... 533
15.3.2 Initialization after a Hardware Reset.................................................................... 536
15.3.3 Transmit Mode ..................................................................................................... 539
15.3.4 Receive Mode....................................................................................................... 546
15.3.5 HCAN Sleep Mode .............................................................................................. 552
15.3.6 HCAN Halt Mode ................................................................................................ 554
15.3.7 Interrupt Interface................................................................................................. 555
15.3.8 DMAC Interface................................................................................................... 556
15.4 CAN Bus Interface ............................................................................................................ 557
15.5 Usage Notes ....................................................................................................................... 558
Section 16 A/D Converter ................................................................................................. 559
16.1 Overview............................................................................................................................ 559
16.1.1 Features ................................................................................................................ 559
16.1.2 Block Diagram...................................................................................................... 561
16.1.3 Pin Configuration ................................................................................................. 562
16.1.4 Register Configuration ......................................................................................... 564
16.2 Register Descriptions......................................................................................................... 565
16.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) ............................................. 565
16.2.2 A/D Control/Status Register 0 (ADCSR0)........................................................... 566
16.2.3 A/D Control Registers 0 and 1 (ADCR0, ADCR1) ............................................. 570
16.2.4 A/D Control/Status Register 1 (ADCSR1)........................................................... 572
16.2.5 A/D Trigger Registers 0 and 1 (ADTRGR0, ADTRGR1) ................................... 575
16.3 CPU Interface .................................................................................................................... 576
16.4 Operation ........................................................................................................................... 577
16.4.1 Single Mode.......................................................................................................... 577
16.4.2 Scan Mode............................................................................................................ 579
16.4.3 Analog Input Sampling and A/D Conversion Time ............................................. 583
16.4.4 External Triggering of A/D Converter ................................................................. 585
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