SH7052 Datasheet, PDF (525/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

14.5.7 Constraints on DMAC Use
• When using an external clock source for the serial clock, update TDR with the DMAC, and
then after the elapse of five peripheral clocks (Pφ) or more, input a transmit clock. If a transmit
clock is input in the first four Pφ clocks after TDR is written, an error may occur (figure
14.26).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
(RXI) interrupt of the SCI as a start-up source.
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: During external clock operation, an error may occur if t is 4 Pφ clocks or less.
Figure 14.26 Example of Synchronous Transmission with DMAC
14.5.8 Cautions on Synchronous External Clock Mode
• Set TE = RE = 1 only when external clock SCK is 1.
• Do not set TE = RE = 1 until at least four Pφ clocks after external clock SCK has changed from
0 to 1.
• When receiving, RDRF is 1 when RE is cleared to zero 2.5 to 3.5 Pφ clocks after the rising
edge of the RxD D7 bit SCK input, but copying to RDR is not possible.
14.5.9 Caution on Synchronous Internal Clock Mode
When receiving, RDRF is 1 when RE is cleared to zero 1.5 Pφ clocks after the rising edge of the
RxD D7 bit SCK output, but copying to RDR is not possible.
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