SH7052 Datasheet, PDF (787/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Increment
address
Start
Set SWE1 bit in FLMCR1
Wait: t_SSWE
Store 128 bytes program data in program
data area and reprogram data area
*4
n=1
Data writes must be performed
in the memory-erased state.
Do not write additional data to
an address to which data is
already written.
m=0
Successively write 128-byte data from
reprogram data area in RAM to flash memory
Write Pulse (t_SP30 or t_SP200)
*1
Subroutine call
See Note 6 for pulse width
Set PV1 bit in FLMCR1
Wait: t_SPV
Perform H'FF dummy-write to verify address
Wait: t_SPVR
Read verify data
*2
n←n+1
Write data = verify data?
No
Yes
6 ≥ n?
Yes
Compute additional-programming data
Transfer additional-programming data
to additional-programming data area
No
*4
m=1
Compute reprogram data
*3
Transfer reprogram data to reprogram data area *4
No
128 byte data verify
complete?
Yes
Clear PV1 bit in FLMCR1
Wait: t_CPV
6 ≥ n?
No
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
*1
Subroutine call
Write Pulse (t_SP10)
No
m = 0?
Yes
Clear SWE1 bit in FLMCR1
Wait: t_CSWE
Programming end
No
n ≥ 1000?
Yes
Clear SWE1 bit in FLMCR1
Wait: t_CSWE
Programming failure
Figure 21.13 Program/Program-Verify Flowchart (1)
761