SH7052 Datasheet, PDF (727/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

20.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset and in
hardware standby mode. It is not initialized in software standby mode. RAMER settings should be
made in user mode or user program mode.
Flash memory area divisions are shown in table 20.5. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— RAMS RAM2 RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
• Bits 15 to 4—Reserved: These bits always read 0. The write value should always be 0.
• Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation
in RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3: RAMS
0
1
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
(Initial value)
701