SH7052 Datasheet, PDF (106/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 6.3 Interrupt Exception Processing Vectors and Priorities
Interrupt Source
NMI
UBC
IRQ0
IRQ1
IRQ2
IRQ3
DMAC0 DEI0
DMAC1 DEI1
DMAC2 DEI2
DMAC3 DEI3
ATU0 ATU01 ITV1
ITV2A
ITV2B
ATU02 ICI0A
ICI0B
ATU03 ICI0C
ICI0D
ATU04 OVI0
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Corre-
sponding
IPR (Bits)
11
H'0000002C to 16
—
H'0000002F
12
H'00000030 to 15
—
H'00000033
64
H'00000100 to 0 to 15 (0) IPRA
H'00000103
(15 to 12)
65
H'00000104 to 0 to 15 (0) IPRA
H'00000107
(11 to 8)
66
H'00000108 to 0 to 15 (0) IPRA
H'0000010B
(7 to 4)
67
H'0000010C to 0 to 15 (0) IPRA
H'0000010F
(3 to 0)
72
H'00000120 to 0 to 15 (0) IPRC
H'00000123
(15 to 12)
74
H'00000128 to 0 to 15 (0)
H'0000012B
76
H'00000130 to 0 to 15 (0) IPRC
H'00000133
(11 to 8)
78
H'00000138 to 0 to 15 (0)
H'0000013B
80
H'00000140 to 0 to 15 (0) IPRC
H'00000143
(7 to 4)
84
H'00000150 to 0 to 15 (0) IPRC
H'00000153
(3 to 0)
86
H'00000158 to
H'0000015B
88
H'00000160 to 0 to 15 (0) IPRD
H'00000163
(15 to 12)
90
H'00000168 to
H'0000016B
92
H'00000170 to 0 to 15 (0) IPRD
H'00000173
(11 to 8)
Priority
within IPR
Setting Default
Range Priority
—
High
—
—
—
—
—
↑1
↓2
↑1
↓2
↑1
↓2
↑1
↓2
Low
80