SH7052 Datasheet, PDF (14/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

8.2.1 Bus Control Register 1 (BCR1)............................................................................ 122
8.2.2 Bus Control Register 2 (BCR2)............................................................................ 123
8.2.3 Wait Control Register (WCR).............................................................................. 126
8.2.4 RAM Emulation Register (RAMER) ................................................................... 128
8.3 Accessing External Space.................................................................................................. 130
8.3.1 Basic Timing ........................................................................................................ 130
8.3.2 Wait State Control................................................................................................ 131
8.3.3 CS Assert Period Extension.................................................................................. 133
8.4 Waits between Access Cycles ........................................................................................... 134
8.4.1 Prevention of Data Bus Conflicts ......................................................................... 134
8.4.2 Simplification of Bus Cycle Start Detection ........................................................ 135
8.5 Bus Arbitration .................................................................................................................. 136
8.6 Memory Connection Examples ......................................................................................... 137
Section 9 Direct Memory Access Controller (DMAC).......................................... 139
9.1 Overview............................................................................................................................ 139
9.1.1 Features ................................................................................................................ 139
9.1.2 Block Diagram...................................................................................................... 140
9.1.3 Register Configuration ......................................................................................... 141
9.2 Register Descriptions......................................................................................................... 142
9.2.1 DMA Source Address Registers 0 to 3 (SAR0 to SAR3) .................................... 142
9.2.2 DMA Destination Address Registers 0 to 3 (DAR0 to DAR3)............................ 143
9.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3) .................. 144
9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3) ............................ 145
9.2.5 DMAC Operation Register (DMAOR) ................................................................ 150
9.3 Operation ........................................................................................................................... 152
9.3.1 DMA Transfer Flow ............................................................................................. 152
9.3.2 DMA Transfer Requests....................................................................................... 154
9.3.3 Channel Priority.................................................................................................... 157
9.3.4 DMA Transfer Types ........................................................................................... 157
9.3.5 Dual Address Mode.............................................................................................. 157
9.3.6 Bus Modes............................................................................................................ 163
9.3.7 Relationship between Request Modes and Bus Modes by DMA Transfer
Category ............................................................................................................... 164
9.3.8 Bus Mode and Channel Priorities......................................................................... 165
9.3.9 Source Address Reload Function ......................................................................... 165
9.3.10 DMA Transfer Ending Conditions ....................................................................... 166
9.3.11 DMAC Access from CPU .................................................................................... 167
9.4 Examples of Use................................................................................................................ 168
9.4.1 Example of DMA Transfer between On-Chip SCI and External Memory.......... 168
9.4.2 Example of DMA Transfer between A/D Converter and On-Chip Memory
(Address Reload On) ............................................................................................ 168
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