SH7052 Datasheet, PDF (265/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Timer Status Registers 2A and 2B (TSR2A, TSR2B)
TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVF2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Bit:
Initial value:
R/W:
7
IMF2H
0
R/(W)*
6
IMF2G
0
R/(W)*
5
IMF2F
0
R/(W)*
4
IMF2E
0
R/(W)*
3
IMF2D
0
R/(W)*
2
IMF2C
0
R/(W)*
1
IMF2B
0
R/(W)*
0
IMF2A
0
R/(W)*
Note: * Only 0 can be written, to clear the flag.
• Bits 15 to 9—Reserved: These bits always read 0. The write value should always be 0.
• Bit 8—Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow.
Bit 8: OVF2A
0
1
Description
[Clearing condition]
(Initial value)
When OVF2A is read while set to 1, then 0 is written to OVF2A
[Setting condition]
When the TCNT2A value overflows (from H'FFFF to H'0000)
• Bit 7—Input Capture/Compare-Match Flag 2H (IMF2H): Status flag that indicates GR2H
input capture or compare-match.
Bit 7: IMF2H
0
1
Description
[Clearing condition]
(Initial value)
When IMF2H is read while set to 1, then 0 is written to IMF2H
[Setting conditions]
• When the TCNT2A value is transferred to GR2H by an input capture
signal while GR2H is functioning as an input capture register
• When TCNT2A = GR2H while GR2H is functioning as an output compare
register
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