SH7052 Datasheet, PDF (825/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 23.4 Register States in Software Standby Mode
On-Chip Peripheral Module Registers Initialized
Interrupt controller (INTC)
—
User break controller (UBC) —
Bus state controller (BSC) —
Direct memory access
controller (DMAC)
All registers
Advanced timer unit (ATU) All registers
Advanced pulse controller
(APC)
Watchdog timer
(WDT)
—
• Bits 7 to 5 (OVF, WT/IT,
TME) of the timer control
status register (TCSR)
• Reset control/status register
(RSTCSR)
• Timer counter (TCNT)
Compare match timer (CMT) All registers
HCAN
Registers other than
MC0[1:8] to MC15[1:8]
MD0[1:8] to MD15[1:8]
Serial communication
interface (SCI)
All registers
A/D converter (A/D)
All registers
Pin function controller (PFC) —
I/O ports (I/O)
—
Flash memory control
registers
All registers (except RAMER)
Power-down state related
—
Registers that Retain Data
All registers
All registers
All registers
—
—
All registers
• Bits 2 to 0 (CKS2 to CKS0)
of TCSR
—
MC0[1:8] to MC15[1:8]
MD0[1:8] to MD15[1:8]
—
—
All registers
All registers
—
• Standby control register
(SBYCR)
• System control register
(SYSCR)
• Module stop control register
(MSTCR)
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