SH7052 Datasheet, PDF (28/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 1.1 SH7052F/SH7053F/SH7054F Features
Item
CPU
Operating states
Multiplier
Features
• Maximum operating frequency: 40 MHz
• Original Hitachi SH-2 CPU
• 32-bit internal architecture
• General register machine
 Sixteen 32-bit general registers
 Three 32-bit control registers
 Four 32-bit system registers
• Instruction execution time: Basic instructions execute in one state
(25 ns/instruction at 40 MHz operation)
• Address space: Architecture supports 4 Gbytes
• Five-stage pipeline
• Operating modes
 Single-chip mode
 8/16-bit bus expanded mode
• Mode with on-chip ROM
• Mode with no on-chip ROM
• Processing states
 Reset state
 Program execution state
 Exception handling state
 Bus-released state
 Power-down state
• Power-down state
 Sleep mode
 Software standby mode
 Hardware standby mode
 Module standby
• 32 × 32 → 64 multiply operations executed in two to four cycles
32 × 32 + 64 → 64 multiply-and-accumulate operations executed in two to
four cycles
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