SH7052 Datasheet, PDF (390/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

Timing of IIF Setting by Interval Timer: When 1 is generated by ANDing the rise of bit 10 to
13 in free-running counter TCNT0L with bit ITVE0 to ITVE3 in the interval interrupt request
register (ITVRR), the IIF bit is set to 1 in the timer status register (TSR).
The timing in this case is shown in figure 10.41. TCNT0 value N in the figure is the counter value
when TCNT0L bit 6 to 13 changes to 1. (For example, N = H'00000400 in the case of bit 10,
H'00000800 in the case of bit 11, etc.)
CK
TCNT input clock
TCNT0
N–1
N
Internal interval signal
Interrupt status flag
IIF
Interrupt request signal
Figure 10.41 Timing of IIF Setting Timing by Interval Timer
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