SH7052 Datasheet, PDF (448/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

12.3.2 Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval
timer interrupt (ITI) is generated each time the timer counter overflows. This function can be used
to generate interval timer interrupts at regular intervals (figure 12.5).
TCNT value
H'FF
Overflow
Overflow
Overflow
Overflow
H'00
Time
WT/IT = 0
ITI
ITI
ITI
ITI
TME = 1
ITI: Interval timer interrupt request generation
Figure 12.5 Operation in Interval Timer Mode
12.3.3 Clearing Software Standby Mode
The watchdog timer has a special function to clear software standby mode with an NMI interrupt.
When using software standby mode, set the WDT as described below.
Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to
stop the watchdog timer counter before entering software standby mode. The chip cannot enter
software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the
counter overflow interval is equal to or longer than the oscillation settling time. See section 24.3,
AC Characteristics, for the oscillation settling time.
Recovery from Software Standby Mode: When an NMI request signal is received in software
standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the
rate selected by bits CKS2 to CKS0 before software standby mode was entered. When TCNT
overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock
signals are supplied to the entire chip and software standby mode ends.
For details on software standby mode, see section 23, Power-Down State.
422