SH7052 Datasheet, PDF (301/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Bit 1—Cycle Register Compare-Match Interrupt Enable 6B/7B (CME6B/CME7B): Enables or
disables interrupt requests by CMFxB in TSR6 or TSR7 when CMFxB is set to 1. Setting the
DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt
request.
Bit 1: CMExB
0
1
x = 6 or 7
Description
CMIxB interrupt requested by CMFxB is disabled
CMIxB interrupt requested by CMFxB is enabled
(Initial value)
• Bit 0—Cycle Register Compare-Match Interrupt Enable 6A/7A (CME6A/CME7A): Enables or
disables interrupt requests by CMFxA in TSR6 or TSR7 when CMFxA is set to 1. Setting the
DMAC while interrupt requests are enabled allows the DMAC to be activated by an interrupt
request.
Bit 0: CMExA
0
1
x = 6 or 7
Description
CMIxA interrupt requested by CMFxA is disabled
CMIxA interrupt requested by CMFxA is enabled
(Initial value)
Timer Interrupt Enable Register 8 (TIER8)
TIER8 controls enabling/disabling of channel 8 one-shot pulse interrupt requests.
Bit:
Initial value:
R/W:
15
14
13
12
11
OSE8P OSE8O OSE8N OSE8M OSE8L
0
0
0
0
0
R/W R/W R/W R/W R/W
10
OSE8K
0
R/W
9
OSE8J
0
R/W
8
OSE8I
0
R/W
Bit: 7
6
5
4
3
2
1
0
OSE8H OSE8G OSE8F OSE8E OSE8D OSE8C OSE8B OSE8A
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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