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SH7052 Datasheet, PDF (132/919 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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7.2.4 User Break Control Register (UBCR)
Bit: 15
14
13
12
11
10
9
8
â
â
â
â
â
â
â
â
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
â
â
â
â
â
CKS1 CKS0 UBID
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or
disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the
event of a break condition match.
UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not
initialized in software standby mode.
⢠Bits 15 to 3âReserved: These bits always read 0. The write value should always be 0.
⢠Bits 2 and 1âClock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the
UBCTRG signal output in the event of a condition match.
Bit 2: CKS1
Bit 1: CKS0
0
0
1
1
0
1
Note: Ï: Internal clock
Description
UBCTRG pulse width is Ï
UBCTRG pulse width is Ï/4
UBCTRG pulse width is Ï/8
UBCTRG pulse width is Ï/16
(Initial value)
⢠Bit 0âUser Break Disable (UBID): Enables or disables user break interrupt request generation
in the event of a user break condition match.
Bit 0: UBID
0
1
Description
User break interrupt request is enabled
User break interrupt request is disabled
(Initial value)
106
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