SH7052 Datasheet, PDF (633/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3 Register Descriptions
18.3.1 Port A IO Register (PAIOR)
Bit: 15
14
13
12
11
10
9
8
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 7
6
5
4
3
2
1
0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/RxD0 to
PA0/TI0A. PAIOR is enabled when port A pins function as general input/output pins (PA15 to
PA0) or ATU input/output pins, and disabled otherwise. For bits 3 to 0, when ATU input capture
input is selected, the PAIOR bits should be cleared to 0.
When port A pins function as PA15 to PA0 or ATU input/output pins, a pin becomes an output
when the corresponding bit in PAIOR is set to 1, and an input when the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
18.3.2 Port A Control Registers H and L (PACRH, PACRL)
Port A control registers H and L (PACRH, PACRL) are 16-bit readable/writable registers that
select the functions of the 16 multiplex pins in port A. PACRH selects the functions of the pins for
the upper 8 bits of port A, and PACRL selects the functions of the pins for the lower 8 bits.
PACRH and PACRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on
reset), and in hardware standby mode. They are not initialized in software standby mode or sleep
mode.
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