SH7052 Datasheet, PDF (625/919 Pages) Renesas Technology Corp – SuperHTM RISC engine

AUDCK
AUDSYNC
AUDATAn
0000 1110 A3–A0
DIR
Input/output switchover
A31–A28 D3–D0
D31–D28
0000
Not ready
Input
0001
Ready
Output
0001 0001
Ready Ready
Figure 17.6 Example of Write Operation (Longword Read)
AUDCK
AUDSYNC
AUDATAn
0000 1010 A3–A0
DIR
Input
Input/output switchover
A31–A28
0000
Not ready
0101
Ready
(Bus error)
0101 0101
Ready Ready
(Bus error) (Bus error)
Output
Figure 17.7 Example of Error Occurrence (Longword Read)
17.5 Usage Notes
17.5.1 Initialization
The debugger’s internal buffers and processing states are initialized in the following cases:
1. In a power-on reset
2. In hardware standby mode
3. When AUDRST is driven low
4. When the AUDSRST bit is set to 1 in the SYSCR register (see section 23.2.2)
5. When the MSTOP3 bit is set to 1 in the MSTCR register (see section 23.2.3)
17.5.2 Operation in Software Standby Mode
The debugger is not initialized in software standby mode. However, since the
SH7052F/SH7053F/SH7054F’s internal operation halts in software standby mode:
1. When AUDMD is high (RAM monitor mode): Ready is not returned (Not Ready continues to
be returned)
However, when operating on an external clock, the protocol continues.
2. When AUDMD is low (PC trace): Operation stops. However, operation continues when STBY
is released.
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