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SH7052 Datasheet, PDF (171/919 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
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9.2.4 DMA Channel Control Registers 0 to 3 (CHCR0 to CHCR3)
DMA channel control registers 0 to 3 (CHCR0 to CHCR3) are 32-bit readable/writable registers
that designate the operation and transmission of each channel. CHCR register bits are initialized to
0 by a power-on reset and in standby mode.
Bit: 31
30
29
28
27
26
25
24
â
â
â
DI
â
â
â
RO
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W*2
R
R
R
R/W*2
Bit: 23
22
21
20
19
18
17
16
â
â
â
RS4 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R/W
R/W R/W*1 R/W
Bit: 15
â
Initial value: 0
R/W: R
14
13
12
11
â
SM1 SM0
â
0
0
0
0
R
R/W R/W
R
10
9
8
â
DM1 DM0
0
0
0
R
R/W R/W
Bit: 7
6
5
4
3
2
1
0
â
â
TS1
TS0
TM
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R/W
R/W
R/W
R/W R/(W)*1 R/W
Notes: 1. TE bit: Allows only a 0 write after reading 1.
2. The DI and RO bits may be absent, depending on the channel.
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